An interesting piece looking at estimating wafer costs for each of TSMCs nodes.
The bit I found interesting is when you compare a theoretical chip price across nodes.
But even at current costs it makes a great sense for makers of highly-complex chips to use TSMC’s leading-edge process because of its high transistor density as well as performance. Based on the numbers provided, it costs $238 to make a 610mm2 chip using N5 and $233 to produce the same chip using N7.
Even the staggeringly high cost of a N5 wafer is economical because of the increased density. That’s not something I fully appreciated.
If ASML’s production capacity is as expected for 2020 and 2021 this means TSMC should retain its dominant position in small feature sizes because there simply wont be enough capacity going anywhere else.
If EUV lithography is going to be pretty much essential for any advanced process going onwards this advantage should be almost insurmountable in the near term.
On new N3 and N2 process
So while it looks like we can expect TSMC to retain the advantage on feature sizes, there is a potential bump in 2022 when they will still be using FinFET while Samsung will have moved to GAA transistors. It will be interesting to see if Samsung (and its customers) can capitalise on their GAA advantage before TSMC’s N2 node arrives in 2023 which is expected to be using GAA transistors.
My biggest concerns at this point are unchanged:
Global downturn in semiconductor demand
Samsung’s lead in GAA transistors
I am now also a bit worried that TSMC is getting very expensive with a market cap of ~$400bn and a trailing p/e of ~25, hopefully it can grow into that valuation. On balance I’m happy to to hold TSMC despite the significant increase in price, it feels somewhat justified.
So from a quick look I think TSMC bought about 25 EUV scanners in 2020 from a total spend of about 18bn so very crudely about 20-25% capex went to ASML EUV.
So that might put a 100bn spend at around 20-25bn on EUV for perhaps 120-130 scanners. Even with ASML set to double volumes that pretty much all their capacity into 2023.
For ArF immersion DUV ASML don’t have a complete monopoly, so Nikon might take a bit.
It’s hard to know how many layers of EUV vs DUV will be used in future process nodes. I think for N5 it’s about 12 layers of EUV for about 60 layers of DUV. Although generally each EUV layer can replace 10 DUV layers so the trend has been for fewer total layers.
DUV scanners have about double the throughput of EUV so you don’t necessarily need many more units so maybe another 150 DUV units for 7.5-10bn
So maybe in total more like 30bn of this to ASML, it’s hard to see how there is going to be enough capacity with both Intel and Samsung also committed to significant expansion, it feels like someone is going to miss out.
I think it’s all priced in already as ASML has continued to surge during the semiconductor shortage.
Downward slide continues across all Chip manufacturers… any opinions here? Naively i feel chips are like the new oil, and (at least TSMC and AMD) have what looks to me like super healthy balance sheets. What gives?